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cy62136esl mobl ? 2-mbit (128 k 16) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-48147 rev. *d revised june 15, 2011 2-mbit (128 k 16) static ram features very high speed: 45 ns wide voltage range: 2.2 v to 3.6 v and 4.5 v to 5.5 v ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed and power available in pb-free 44-pin thin small outline package (tsop) ii package functional description the cy62136esl is a high performance cmos static ram organized as 128k words by 16 bits. this device features advanced circuit design to provid e ultra low active current. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature t hat reduces power consumption when addresses are not toggling. placing the device into standby mode reduces power consumption by more than 99% when deselected (ce high). the input and output pins (i/o 0 through i/o 15 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high) or during a write operation (ce low and we low). to write to the device, take chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 16 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 16 ). to read from the device, take chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins appears on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory appears on i/o 8 to i/o 15 . see the truth table on page 11 for a complete description of read and write modes. 128 k x 16 ram array i/o 0 ?i/o 7 row decoder a 8 a 7 a 6 a 5 a 2 column decoder a 11 a 12 a 13 a 14 a 15 sense amps data in drivers oe a 4 a 3 i/o 8 ?i/o 15 ce we ble bhe a 16 a 0 a 1 a 9 a 10 logic block diagram [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 2 of 15 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 6 data retention waveform ................................................ 6 switching characteristics ................................................ 7 switching waveforms ...................................................... 8 truth table ...................................................................... 11 ordering information ...................................................... 12 ordering code definitions ..... .................................... 12 package diagram ............................................................ 13 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 3 of 15 pin configuration figure 1. 44-pin tsop ii (top view) [1] 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 a 5 18 17 20 19 27 28 25 26 22 21 23 24 a 6 a 7 a 4 a 3 a 2 a 1 a 0 a 14 a 15 a 8 a 9 a 10 a 11 a 12 a 13 nc oe bhe ble ce we i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 v cc v cc v ss v ss nc 10 a 16 product portfolio product range v cc range (v) [2] speed (ns) power dissipation operating i cc , (ma) standby, i sb2 ( ? a) f = 1mhz f = f max typ [3] max typ [3] max typ [3] max cy62136esl industrial 2.2 v to 3.6 v and 4.5 v to 5.5 v 45 2 2.5 15 20 1 7 notes 1. nc pins are not connected on the die. 2. datasheet specifications are not guaranteed for v cc in the range of 3.6 v to 4.5 v. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 4 of 15 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potential ................?0.5 v to 6.0 v dc voltage applied to outputs in high z state [4, 5] ........................................?0.5 v to 6.0 v dc input voltage [4, 5] ......................................?0.5 v to 6.0 v output current into outputs (low) ............................. 20 ma static discharge voltage ........................................... >2001 v (mil-std-883, method 3015) latch up current ..................................................... > 200 ma operating range device range ambient temperature v cc [6] cy62136esl industrial ?40 c to +8 5 c 2.2 v?3.6 v, and 4.5 v?5.5 v electrical characteristics over the operating range parameter description test conditions 45 ns unit min typ [7] max v oh output high voltage 2.2 < v cc < 2.7 i oh = ?0.1 ma 2.0 ? ? v 2.7 < v cc < 3.6 i oh = ?1.0 ma 2.4 ? ? 4.5 < v cc < 5.5 i oh = ?1.0 ma 2.4 ? ? v ol output low voltage 2.2 < v cc < 2.7 i ol = 0.1 ma ? ? 0.4 v 2.7 < v cc < 3.6 i ol = 2.1 ma ? ? 0.4 4.5 < v cc < 5.5 i ol = 2.1 ma ? ? 0.4 v ih input high voltage 2.2 < v cc < 2.7 1.8 ? v cc + 0.3 v 2.7 < v cc < 3.6 2.2 ? v cc + 0.3 4.5 < v cc < 5.5 2.2 ? v cc + 0.5 v il input low voltage 2.2 < v cc < 2.7 ?0.3 ? 0.6 v 2.7 < v cc < 3.6 ?0.3 ? 0.8 4.5 < v cc < 5.5 ?0.5 ? 0.8 i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma, cmos levels ?1520ma f = 1 mhz ? 2 2.5 i sb1 [8] automatic ce power-down current ? cmos inputs ce > v cc ?? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = f max (address and data only), f = 0 (oe , bhe , ble and we ), v cc = v cc(max) ?17 ? a i sb2 [8] automatic ce power-down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = v cc(max) ?17 ? a notes 4. v il (min) = ?2.0 v for pulse durations less than 20 ns. 5. v ih (max) = v cc + 0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = 3 v, and v cc = 5 v, t a = 25 c. 8. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr spec. other inputs can be left floating. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 5 of 15 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, two-layer printed circuit board 77 ? c/w ? jc thermal resistance (junction to case) 13 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms parameters 2.5 v 3.0 v 5.0 v unit r1 16667 1103 1800 ? r2 15385 1554 990 ? r th 8000 645 639 ? v th 1.20 1.75 1.77 v v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v equivalent to: th venin equivalent all input pulses r th r1 th note 9. tested initially and after any design or proc ess changes that may affect these parameters. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 6 of 15 data retention characteristics over the operating range parameter description conditions min typ [10] max unit v dr v cc for data retention 1.0 ? ? v i ccdr [11] data retention current ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v v cc = 1.0 v ? 0.8 3 ? a t cdr [12] chip deselect to data retention time 0??ns t r [13] operation recovery time 45 ? ? ns data retention waveform figure 3. data retention waveform v cc(min) v cc(min) t cdr v dr > 1.0 v data retention mode t r v cc ce notes 10. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 11. chip enable (ce ) and byte enables (bhe and ble ) need to be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. 12. tested initially and after any design or proces s changes that may affect these parameters. 13. full device operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) > 100 ? s. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 7 of 15 switching characteristics over the operating range parameter [14, 15] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [16] 5 ? ns t hzoe oe high to high z [16, 17] ? 18 ns t lzce ce low to low z [16] 10 ? ns t hzce ce high to high z [16, 17] ? 18 ns t pu ce low to power-up 0 ? ns t pd ce high to ower-down ? 45 ns t dbe ble /bhe low to data valid ? 22 ns t lzbe ble /bhe low to low z [16] 5 ? ns t hzbe ble /bhe high to high z [16, 17] ? 18 ns write cycle [18] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t bw ble /bhe low to write end 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [16, 17] ? 18 ns t lzwe we high to low z [16] 10 ? ns notes 14. test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing ref erence levels of 1.5 v, input pulse levels of 0 to 3 v, and output loading of the specified i ol /i oh as shown in the figure 2 on page 5 . 15. ac timing parameters are subject to byte enable signals (bhe or ble ) not switching when chip is disabled. see application note an13842 for further clarification. 16. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 17. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the outputs enter a high-impedance state. 18. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe , ble or both = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input se tup and hold timing must be referenced to the edge of the sig nal that terminates the write. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 8 of 15 switching waveforms figure 4. read cycle no.1: address transition controlled [19, 20] figure 5. read cycle no. 2: oe controlled [20, 21] previous data valid data valid rc t aa t oha t rc address data out 50% 50% data valid t rc t ace t lzbe t lzce t pu high impedance i cc t hzoe t hzce t pd t hzbe t lzoe t dbe t doe impedance high i sb data out oe ce v cc supply current bhe /ble address notes 19. the device is continuously selected. oe , ce = v il , bhe , ble , or both = v il . 20. we is high for read cycle. 21. address valid before or similar to ce , bhe , ble transition low. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 9 of 15 figure 6. write cycle no 1: we controlled [22, 23, 24] figure 7. write cycle 2: ce controlled [22, 23, 24] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t wc t hzoe data in note 25 t bw t sce data i/o address ce we oe bhe /ble t hd t sd t pwe t ha t aw t sce t wc t hzoe data in t bw t sa ce address we data i/o oe bhe /ble note 25 notes 22. the internal write time of the memory is defined by the overlap of we, ce = v il , bhe and/or ble = v il . all signals are active to initiate a write and any of these signals terminate a write by going inactive. the data input setup and hold timing are referenced to the edge of the signal that terminates the write. 23. data i/o is high impedance if oe = v ih . 24. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 25. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 10 of 15 figure 8. write cycle 3: we controlled, oe low [26] figure 9. write cycle 4: bhe /ble controlled, oe low [26] switching waveforms (continued) data in t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe t bw note 27 ce address we data i/o bhe /ble t hd t sd t sa t ha t aw t wc data in t bw t sce t pwe t hzwe t lzwe note 27 data i/o address ce we bhe /ble notes 26. if ce goes high simultaneously with we = v ih , the output remains in a high impedance state. 27. during this period, the i/os are in output state. do not apply input signals. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 11 of 15 truth table ce [28] we oe bhe ble inputs/outputs mode power hxxx [28] x [28] high z deselect/power-down standby (i sb ) l x x h h high z output disabled active (i cc ) l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) lhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) l h h l l high z output disabled active (i cc ) l h h h l high z output disabled active (i cc ) l h h l h high z output disabled active (i cc ) l l x l l data in (i/o 0 ?i/o 15 ) write active (i cc ) l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write active (i cc ) l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write active (i cc ) note 28. the ?x? (don?t care) state for the chip enable (ce ) and byte enables (bhe and ble ) in the truth table refer to the logic state (either high or low). intermediate voltage levels on these pins is not permitted. [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 12 of 15 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62136ESL-45ZSXI 51-85087 44-pin tsop type ii (pb-free) industrial ordering code definitions temperature grade: i = industrial pb-free package type: zs = 44-pin tsop ii speed grade: 45 ns wide voltage range (3 v and 5 v) process technology: 90 nm bus width = 16 density = 2-mbit family code: mobl sram family company id: cy = cypress cy -zs 621 3 6 e sl i 45 x [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 13 of 15 acronyms document conventions units of measure package diagram figure 10. 44-pin tsop z44-ii, 51-85087 max min. dimension in mm (inch) (optional) can be located anywhere in the bottom pkg ejector mark z a z z z z x a 10.058 (0.396) 10.262 (0.404) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) top view bottom view plane seating 18.517 (0.729) 0.800 bsc 0-5 0.400(0.016) 0.300 (0.012) 1.194 (0.047) 0.991 (0.039) 0.150 (0.0059) 0.050 (0.0020) (0.0315) 18.313 (0.721) base plane 0.10 (.004) 11.938 (0.470) pin 1 i.d. 44 1 11.735 (0.462) 10.058 (0.396) 10.262 (0.404) 22 23 51-85087 *c acronym description ble byte low enable bhe byte high enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius mhz mega hertz ? a micro amperes ? s micro seconds ma milli amperes mm milli meter ns nano seconds % percent pf pico farads ? ohms v volts w watts [+] feedback
cy62136esl mobl ? document #: 001-48147 rev. *d page 14 of 15 document history page document title: cy62136esl mobl ? , 2-mbit (128 k 16) static ram document number: 001-48147 rev. ecn no. orig. of change submission date description of change ** 2615537 vkn/pyrs 12/03/08 new data sheet *a 2718906 vkn 06/15/2009 post to external web *b 2944332 vkn 06/04/2010 added contents added footnote for i sb2 parameter in electrical characteristics added footnote 2 in switching characteristics added footnote related to chip enable and byte enables in truth table updated package diagram updated links in sales, solutions, and legal information *c 3126445 rame 01/03/2011 updated datasheet as per new template added acronyms and units of measure . added ordering code definitions converted all table note to footnote. *d 3283711 rame 06/15/2011 updated functional description (removed ?for best practice recommendations, refer to the cypress application note an1064, sram system guidelines.?). updated in new template. [+] feedback
document #: 001-48147 rev. *d revised june 15, 2011 page 15 of 15 mobl is a registered trademark and more battery life is a trademark of cypress semiconductor. all products and company names me ntioned in this document may be the trademarks of their respective holders. cy62136esl mobl ? ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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